`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	id_ex_u(
    input				clk,
    input				rst_n,
    input               flush,
    input				ena,

    input      [63:0]   Rs1_idu_i,
    output     [63:0]   Rs1_exu_o,

    input      [63:0]   Rs2_idu_i,
    output     [63:0]   Rs2_exu_o,

    input      [63:0]   imm_idu_i,
    output     [63:0]   imm_exu_o,

    input      [63:0]    PC_idu_i,
    output     [63:0]    PC_exu_o,

    input      [5: 0]    uop_code_idu,
    input      [3: 0]    exe_type_idu,

    output     [5: 0]    uop_code_exu,
    output     [3: 0]    exe_type_exu,

    input      [4: 0]   rs1_idu_i,
    output     [4: 0]   rs1_exu_o,

    input      [4: 0]   rs2_idu_i,
    output     [4: 0]   rs2_exu_o,

    input      [4: 0]   ctrl_bus_idu,
    output     [4: 0]   ctrl_bus_exu,

    

    input      [4: 0]   rd_idu_i,
    output     [4: 0]   rd_exu_o
);

            pip_reg  #(.N(6),.zero(6'd0))
            u_uop_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (uop_code_idu),
                    .data_o  (uop_code_exu)
                );
                
            pip_reg  #(.N(4),.zero(4'd0))
            u_ctrl_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (ctrl_bus_idu),
                    .data_o  (ctrl_bus_exu)
                );
            
            pip_reg  #(.N(4),.zero(4'd0))
            u_exe_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (exe_type_idu),
                    .data_o  (exe_type_exu)
                );
            
            pip_reg  #(.N(64),.zero(64'd0))
            u_Rs1_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (Rs1_idu_i),
                    .data_o  (Rs1_exu_o)
                );
            
            pip_reg  #(.N(64),.zero(64'd0))
            u_Rs2_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (Rs2_idu_i),
                    .data_o  (Rs2_exu_o)
                );
            
            pip_reg  #(.N(64),.zero(64'd0))
            u_imm_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (imm_idu_i),
                    .data_o  (imm_exu_o)
                );
            
            pip_reg  #(.N(64),.zero(64'd0))
            u_Rd_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i   (Rd_idu_i),
                    .data_o   (Rd_exu_o)
                );
            
            pip_reg  #(.N(64),.zero(64'd0))
            u_PC_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i   (PC_idu_i),
                    .data_o   (PC_exu_o)
                );

            pip_reg  #(.N(5),.zero(5'd0))
            u_rs1_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (rs1_idu_i),
                    .data_o  (rs1_exu_o)
                );
            pip_reg  #(.N(5),.zero(5'd0))
            u_rs2_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (rs2_idu_i),
                    .data_o  (rs2_exu_o)
                );
            pip_reg  #(.N(5),.zero(5'd0))
            u_rd_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (rd_idu_i),
                    .data_o  (rd_exu_o)
                );

endmodule